Currently, as low-temperature polysilicon display substrates have higher drive capability compared with amorphous silicon display substrates, higher display quality can be easily obtained, and hence low-temperature polysilicon display substrates are more and more favored by users. FIG. 1 is a schematic structural view of a typical top-gate array substrate. The array substrate comprises a transparent substrate 101′ such as glass or the like, a buffer layer 102′, a polysilicon active layer 103′, a gate insulating layer 104′, a gate metal layer 105′ and an interlayer insulating layer 106′. In the process of etching a through hole, a mask is formed on the interlayer insulating layer 106′ by a photolithography process; and a region to be etched is etched and removed by dry etching, so as to form the through hole. In the subsequent process, a metal can be deposited into the through hole so as to connect with the polysilicon active layer.
As the difference of the sum of the thickness of the gate insulating layer 104′ and the thickness of the interlayer insulating layer 106′ from the thickness of the active layer is very large (the ratio of both is more than 10:1), the etching process is very difficult. Moreover, whether etching is conducted immediately till the surface of the polysilicon active layer cannot be easily and effectively monitored, and hence the active layer tends to be over-etched. Therefore, the production yield of the polysilicon substrate can be reduced. Particularly when the dimension of the substrate is large, the etching degree of the entire substrate can be more difficultly determined.
Of course, other films beside the active layer also have the problem of over-etching in the etching process.